1. Field of the Invention
The present invention refers generally to a high-frequency diode and particularly to a high-frequency diode requiring a lower bias in the blocking state than high-frequency diodes according to the prior art.
2. Description of the Related Art
Silicon high-frequency switches are often realized with PIN diodes. This results from the structure of the PIN diodes favorable for high-frequency technical applications, as it is, for example, shown in FIG. 3. Thereby, the PIN diode comprises a half-isolating substrate 300, into which a well 302 is embedded, which has an n-doped semiconductor material with a high n+ dopant concentration compared to the half-isolating substrate 300 (buried layer n-cathode). Further, a second semiconductor area is disposed in a central area 304 of a surface 306 of the well 302, which comprises an n-doped semiconductor material with a lower dopant concentration than the semi-isolating substrate 300 (n intrinsic zone, I-zone). Further, a third semiconductor area 312 is disposed on a surface 310 of the second semiconductor area 308, which comprises a p-doped semiconductor material with a high p+-doped concentration (p-anode). The third semiconductor area 312 and the second semiconductor area 308 are bounded on the sides by a boundary structure 314, wherein the boundary structure 314 further extends into the first semiconductor area 302. The boundary structure 314 is formed by an oxide filled isolation trench (oxide filled trench). A filling material 316 is disposed on the side of the boundary structure 314 opposing the second semiconductor area 308 and the third semiconductor area 312, which has a recess 320 in the marginal area 318. Further, a contacting structure 322 is disposed in the recess 320, which comprises sub-areas 324 of electrically conductive material and sub-areas 326 of electrically isolating material. The electrically conductive sub-areas 324 are further electrically conductively connected to the first semiconductor area 302, so that the first semiconductor area 302 can be contacted electrically conductively from a contact point 328 via the contacting structure 322. Further, a cover layer 330 is disposed at least partly on the boundary structure 314 as well as the filling material 316.
The favorable characteristics by which a PIN diode is optimally suited as a high-frequency switch, are particularly given by the weakly n-doped second semiconductor area 308, which is disposed between the highly n-doped first semiconductor area 302 and the highly p-doped third semiconductor area 312. When applying a blocking voltage, a space charge region forms between a pn-junction, wherein the space charge region has a space charge region width in the respectively differently doped semiconductor areas which depends on the dopant concentration in the respective semiconductor area. Since, when applying a blocking voltage between the first semiconductor area 302 and the third semiconductor area 312 between the first semiconductor area 302 and the second semiconductor area 308, a space charge region results which has a large width in the second semiconductor area 308 due to the low charge carrier density, the PIN diode illustrated in FIG. 3 thus forms a low blocking capacity due to the broad space charge region between the first semiconductor area 302 and the second semiconductor area 308, whereby the favorable blocking characteristics of the PIN diodes as high-frequency switch are effected.
WLAN systems require an antenna switch, which can be used for two frequency bands at 2.5 and 5.5 GHz, has short switching times of 80 ns and copes with powers of up to 1 W. The PIN diode illustrated in FIG. 3 is suitable both for realizing integrated circuits and discrete flip-chip diodes. Classical diode structures with wire bonding and backside contact are not suitable any more for the high frequencies. Thus, a buried-layer cathode 302 with trench sinker in the shape of the illustrated contacting structure 322 is used, which leads the cathode contact towards the top. Further, the diode is surrounded by a trench in the form of the boundary structure 314, which keeps the injection volume small and thus the switching time short. To keep the injection volume small and thus the switching times short, a PIN diode according to FIG. 3 has additionally a thickness 332 of merely 7 μm and a width 334 of merely 50 μm. Further, the contacting structure 322 has also sub-areas of an isolating material, whereby the volume of the conductive material 326 can be reduced and thus the shortening of the switching time of the PIN diode is possible by reducing the number of charge carriers (for example electrons) to be moved.
The diode does fulfill the above requirement, however, it is disadvantageous that it requires a high bias voltage of almost the value of the high-frequency amplitude, which is 10 V at 1 Watt, during blocking operation with 1 W power level. In other words, for blocking the current flow, the PIN diode requires a bias which corresponds to approximately the height of the high-frequency amplitude which is to be blocked. Apart from a time voltage curve 410 and a time current curve 412, the oscillogram in the lower sub-image of FIG. 4 shows also a DC voltage level of 8 V, an amplitude of the fundamental wave of 10 V and level distances of 64, 68 and 74 dB for the H2, H3 and H4 harmonics. A simulation of the blocking behavior (see FIG. 4, lower sub-image) shows that with 8 V bias the forward current is suppressed so far that a sufficiently large harmonic distance of 60 dB is kept.
The left upper sub-image of FIG. 4 shows a doping profile, which represents a hole concentration 420 of the p-anode at the left margin as well as an electron concentration 422 of the n-cathode (buried layer n-cathode) at the right margin. Further, the doping profile shows that charge carriers, i.e. electrons and/or holes, already enter the second semiconductor area (I-zone), wherein the second semiconductor area is represented in the central area of the doping profile. The current flowing thereby is too small to cause a mentionable isolation deterioration and to affect the harmonic behavior. In the right upper sub-image, the potential curve in the third, second and first semiconductor area as well as in the barrier area is illustrated at different operating times.
One possible process for reducing the required bias is to make the I-zone of the PIN diode long and thus to reduce the turn-on speed of the PIN diode so far that a time period of a positive half-wave of a high-frequency modulation is not sufficient for the PIN diode to turn on. In other words, the thickness 332 of the second semiconductor area 308 illustrated in FIG. 3 is enlarged such that the charge carriers cannot drift through the second semiconductor area 308 during the positive half-wave of the high-frequency modulation and thus switching through of the PIN diode is prevented. Thus, the thickness 332 of the second semiconductor area 308 is dependent on the operating frequency of the PIN diode. However, it is one disadvantage of this method that the switching time of the PIN diode switch will become longer.